This invention relates to signal clocking and more specifically to signal clocking of digtial video to substantially reduce peak electromagnetic emissions.
Digital television technology has become increasingly popular within the last few years. However, digital televisions employ wide, high speed digital busses that produce electromagnetic interference (EMI) signals, which may exceed the emission limits set forth by government regulatory standards, such as those set by Federal Communications Commission (FCC).
A large component of EMI in digital televisions is introduced by the harmonics of the video sampling clock, and the wide data buses associated with that clock. Those harmonics can cause major EMI problems in the digital processing stage of the television set, as well as xe2x80x9cleakingxe2x80x9d through to the following analog stages. Typically, in order to comply with the EMI emission requirements, many digital TVs employ electromagnetic shielding techniques. However, these shielding techniques add to the overall cost of the TV set. They also add to the overall weight and size of the TV set.
Furthermore, EMI leaking signals that travel through the analog stage of the TV set are amplified by the cathode ray tube (CRT) driver electronic. The amplified EMI signals can then radiate very efficiently through the large aperture of the CRT itself, where shielding, or other methods of reducing electromagnetic interference (EMI) is almost impossible without degradation of the picture quality.
Thus, there is a need for a system and a method that reduces electromagnetic interference emissions in a digital TV without the shortcomings described above.
In accordance with one embodiment of the invention a spread spectrum pixel clock signal is generated to spread out the frequency bandwidth within which the peak emission of an electromagnetic interference signal occurs, so as to decrease the peak electromagnetic emission level. In one embodiment of the invention, this objective is accomplished by employing the horizontal synchronization signal of a video image to generate a periodic waveform that modulates the pixel clock reference input, such that clock signal pulses are spread out within each scan line. The modulation signal is however synchronized with the horizontal synchronization signal also referred to as the horizontal scanning signal so that each pixel location remains consistent in the horizontal and time domain.
In accordance with one embodiment of the invention, the pixel clock reference input signal is frequency modulated (FM) by a signal which is a coherent harmonic of the fundamental frequency of the horizontal scanning signal.
In accordance with another embodiment of the invention, a waveform synthesizer is configured to receive the horizontal synchronization signal of a video signal from a digital video transmission bus so as to generate the required frequency modulation FM signal. A pixel clock reference signal is provided to a phased lock loop (PLL) circuit to generate a pixel clock reference signal. The PLL is also configured to receive the frequency modulation signal via a high pass filter so as to vary the frequency of the pixel clock reference input in accordance with the waveform of the signal generated by the waveform synthesizer. As such the PLL functions as a modulating circuit that modulates the pixel clock signal received from pixel clock generator 116 by a modulating signal generated by waveform synthesizer 120. The frequency modulated signal generated at the output port of the phase lock loop is then provided instead of the pixel clock reference signal for driving the following stages of the video system path. This frequency modulated signal referred to as the spread spectrum pixel clock signal substantially reduces the EMI peak emission in the digital video image bus.